When Phison Electronics CEO Pua Khein-Seng publicly stated that “NAND production capacity for 2026 has already been fully booked,” the entire semiconductor supply chain was pushed into a new round of discussion.

SSD read and write operations follow unique rules at the physical level, and these fundamental rules determine its performance. We can understand its core principles through the following points.

HBM differs from traditional DDR memory in its 3D TSV (Through-Silicon Via) vertical interconnection design. Multiple DRAM dies are stacked vertically and connected through silicon vias, then packaged together with a logic die (typically a GPU or AI accelerator) on a silicon interposer.

According to public reports, flash memory giant SanDisk announced a significant increase in NAND flash contract prices for November, with a rise of up to 50%. This news immediately attracted the attention of the entire storage supply chain and led the industry to reconsider future market trends.

We can imagine an SSD as an efficiently run smart city. The NAND flash chips that store data are like land and buildings in the city, providing physical space for data storage. The SSD controller is like the city government and the traffic control center.