HBM differs from traditional DDR memory in its 3D TSV (Through-Silicon Via) vertical interconnection design. Multiple DRAM dies are stacked vertically and connected through silicon vias, then packaged together with a logic die (typically a GPU or AI accelerator) on a silicon interposer.

According to public reports, flash memory giant SanDisk announced a significant increase in NAND flash contract prices for November, with a rise of up to 50%. This news immediately attracted the attention of the entire storage supply chain and led the industry to reconsider future market trends.

We can imagine an SSD as an efficiently run smart city. The NAND flash chips that store data are like land and buildings in the city, providing physical space for data storage. The SSD controller is like the city government and the traffic control center.

High-Bandwidth Flash is not an entirely new storage medium, but rather a clever architectural innovation. Its core idea is to combine the 3D NAND flash memory commonly found in our daily lives (used in phones and solid-state drives) with the advanced packaging and interconnection technology of HBM, which is commonly used in high-performance computing.

n 2025, artificial intelligence (AI) has moved beyond early-stage experimentation and initial rollout, entering a phase of broad application and large-scale industrial deployment. Whether it is the training of ultra-large-scale models or low-latency inference in business applications, AI’s usage scenarios and data volumes are growing explosively.